1. Field of the Invention
The present invention relates to a method for the global planarization of surfaces of semiconductor integrated circuits wherein an auxiliary layer made of a dielectric is etched back.
2. Description of the Prior Art
A similar method is disclosed, for example, in EP 0 416 165. In this method, a locally planarized silicon-dioxide insulating layer of a given thickness is first deposited on the patterned layer to be planarized. Then, photoresist patterns are formed as an auxiliary level in an inverse pattern of the underlying pattern level. A further, highly adhering, auxiliary layer to be planarized is deposited, and the whole structure is subjected to an anisotropic etching process in which practically all auxiliary layers and the layer to be planarized are etched. Any remainder of the photoresist pattern that may be left after the etching is stripped away.
In view of the current trend toward shrinkage of feature-sizes and the resulting requirement for an increase in the optical resolution of the photolithographic equipment, topographical height variations on the semiconductor circuits are becoming increasingly less acceptable, since the depth of field of the photolithographic equipment becomes insufficient as its numerical aperture and resolution increases. As a result, unwanted portions of the photoresist may remain after the photomasking process. Such problems are inevitably compounded as the number of interconnection levels increases. Greater layer thicknesses also have detrimental effects, and if several interconnection levels are present, the layer thicknesses cannot be arbitrarily reduced.
So called local planarizations are known, which are processes in which a glass layer, for example, is caused to flow in an annealing step, or processes in which a glass layer is first deposited and then anisotropically etched back.
There are still other methods of global planarization, such as mechanical grinding of the oxide layers. They have the disadvantage of not only requiring an additional grinding device but also planarizing stepper targets. An alternative is the method referred to above.
It is the object of the invention to avoid the disadvantages of the processes described and provide a simplified sequence of steps for global planarization using conventional, proven fabrication techniques and apparatus.
The object is attained by the invention set forth in claim 1. Further advantageous aspects of the invention are characterized in the subclaims.